In a nonvolatile memory device such as a flash EEPROM(Electrically Erasable Programmable Read Only Memory), control gates are formed along both sides of a bit line, which are electrically connected on the outside of cell arrays.
FIG. 1 shows a layout illustrating arrays of a Virtual Ground Split Gate Cell, which is a flash EEPROM cell of a conventional nonvolatile memory device.
An active region A separated by a filed region B is defined to include a plurality of bit lines C, a plurality of virtual ground lines D, channels of a plurality of floating gates 4, and channels of a plurality of select gates 11. The bit lines C are formed longitudinally to include a drain contact E. The virtual ground lines D are formed longitudinally to include a source contact F. A plurality of unit cells are formed between the drain contact E and the source contact F. Between the bit lines C, the virtual ground lines D are formed one by one. Control gates 6 are formed along both sides of the bit lines C. The select gates 11 are formed transversely to overlap with the floating gates 4 and the control gates 6.
The process of manufacturing a conventional nonvolatile memory device will be described briefly by reference to FIG. 1A, a sectional view of the device along line X1--X1 in FIG. 1, and Fig. 1B, an enlarged sectional view of the device along line X2--X2 in FIG. 1.
The active region A and the filed region B are defined by a device isolation process. A filed oxide film 2 is formed on a silicon substrate 1 in the filed region B by an oxidation process. After a tunnel oxide film 3, a first polysilicon layer 4, interlayer insulation film 5 and a second polysilicon layer 6 are deposited on the entire silicon substrate 1, the first and second polysilicon layers 4 and 6 are patterned by a self-aligned etching method, thereby forming the floating gates 4 and the control gates 6. A source 7 and a drain 8 are formed by a source/drain mask work and an ion implantation process. Then, a diffusion layer 8A connecting the drain 8 of each of the unit cells and a diffusion layer(not shown) connecting the source 7 of each of the unit cells are formed simultaneously, thereby forming the bit lines C and the virtual ground lines D. An insulation film 9 is formed on the control gate 6. A select gate oxide film 10 is formed on the silicon substrate 1 of a select gate channel. A third polysilicon layer 11 is deposited on the entire structure. The third polysilicon layer 11 is patterned by a select gate mask work and an etching process, thereby forming the select gates 11.
The control gates 6 are formed along the sides of the bit lines C, which are electrically connected outside the cell arrays. If the device area is reduced for the purpose of higher integration, the control gates 4 cannot be made continuous due to the step coverage caused by the underlying layers and the subsequent processes such as the oxidation process resulting in an adverse effect on the productivity of the device.